Curriculum Vitae

I am a digital hardware designer with special interest on processor architecture and performance optimisation, as well as in research and scientific communication. I have several years of experience designing and leading different units in MIPS and Arm CPUs.

Employment

Senior CPU Design Engineer
Arm (CPU Group)
July 2017 – June 2022 (Cambridge, UK)

  • Senior designer in charge of the development of Embedded Trace Macrocell (ETM) unit for next-generation R-class Arm processors (Cortex R©-R82), optimised for performance and power efficiency.
  • Senior designer responsible for the implementation of safety features (Dual-Core Lock Step) for next-generation R-class Arm processors.
  • Line manager to an intern and 2 graduate engineers, in charge of supervising their early career development.

Leading Hardware Design Engineer
Imagination Technologies (MIPS Division)
July 2016–July 2017 (Kings Langley, UK)

  • Team lead in charge of the Instruction Fetch Unit of MIPS processors (I6400, I6500, I6500-F). Responsible for design, implementation and verification of the unit, ensuring that it met the standards of quality, performance and power consumption.
  • Lead engineer in charge planning, scheduling and resourcing of the PDtrace™ unit for next-generation multi-threaded MIPS processors (I6400, I6500, I6500-F).
  • Responsible for a team of 7 people working on PDtrace and 3 people working on the Fetch Unit.
  • Responsible for ensuring the development and verification of PDtrace and IFU units met the requirements for functional safety and ISO 26262 compliance.
  • Design and maintenance of custom scripts and framework for regression management, simulation and coverage collection (Python).
  • Involvement in the University Programme as developer and trainer (MIPSfpga programme).

Hardware Design Engineer
Imagination Technologies (MIPS Division)
December 2013–June 2016 (Kings Langley, UK)

  • Team lead in charge of the Instruction Fetch Unit of MIPS processor (I6400).
  • Responsible for a team of 3 people working on the Fetch Unit. Responsible for a young engineer placement (3 months) and a university professor sabbatical (6 months).
  • Design of verification framework for unit level testing (Verilog, SystemVerilog, UVM) and constraint-randomized programs for core-level verification (Perl, MIPS ASM).
  • Design of a custom scripted framework for regression management similar to ExecMan, vManager (Python).
  • Involvement in the University Programme as developer and trainer (MIPSfpga programme).

Teacher
Intecysa School (Aramaia S.L.)
July 2006–August 2008 (Madrid, Spain)

Over the span of two years, I taught Automaton Theory and Finite Languages, and Processor Structure and Design to more than a dozen student groups in both semester-long and summer-intensive courses.